1. Field of the Invention
The present invention relates generally to digital circuit architecture, and more specifically to a manner of flushing a stored bit to a nearby cell in a scannable register.
2. Description of the Related Art
A scan path is a technique circuit designers use to increase the controllability and observability of a logic circuit by incorporating “scan registers” into the circuit. Normally, these scan registers act like flip-flops or other latches but circuit designers can switch the scan registers into a “test” mode where the collection of scan registers becomes one long shift register. Scan registers are serial logic circuits. A serial logic circuit operates based on a timing signal or a clock signal. Conventional scan registers move data in two ways. The first way, is to move all bits stored to an adjacent cell of the scan register. The second way, is to read one or more bits out of the register, and then write one or more bits.
A clock signal is a timing signal that alternates between binary 1 and binary 0 at a frequency. The clock signal may have sharp transitions that are brief, followed by an interval of binary 1 or 0. Generally, a clock signal is periodic with small acceptable tolerances for changes in the period between transitions.
Each latch of a scan register stores a logic voltage. A logic voltage is a voltage range that is accepted to mean a binary 1 or a voltage range that is accepted to mean a binary 0. A circuit designer establishes the voltage range with reference to a ground voltage of an overall circuit. Ground voltage is a voltage that a circuit designer makes available in activated circuit boards that occurs, within some tolerances, at an equal voltage throughout the device that a ground voltage conductor reaches. Typically, accepted voltages for a binary 1 are 0.9 to 1.0 volts. Typically, accepted voltages for a binary 0 are 0.0 to 0.1 volts. The binary 1 is complementary to the binary 0. The binary 0 is complementary to the binary 1.
A bit is a logical description of a voltage that is stored at a circuit node. A latch is a circuit that maintains a voltage at a circuit node. A circuit node is a contiguous conductor that may have multiple branches. A latch may maintain a complementary voltage at a complementary circuit node.
A line or node is a contiguous conductor, and may have several branches. It is sometimes helpful to have a way to flush a bit stored on a conductor of a latch to a nearby latch. Unlike copying bits to adjacent latches in a serial scan, a flush copies a selected sub-set of bits or voltages in a subset of latches to another subset of latches. In addition, flushing from one subset to another subset is most beneficial when the flush occurs in a single clock-cycle of a circuit's operation.
A gate is a transistor having an input line, a gate signal line, and an output line, wherein the gate couples a voltage present on the input line to an output line, upon application of, for example, a 1 bit to the gate signal line. A semiconductor couples the gate input line and the gate output line, wherein the semiconductor is a component of the gate that intervenes between the input line and the output line. A binary 1 voltage applied to the gate signal line establishes a voltage in the semiconductor that permits the output line to receive the voltage of the input line. For example, a gate is a metal-oxide semiconductor field effect transistor.
An AND gate is a logic circuit that has at least two inputs each capable of receiving a bit, wherein the output of the AND gate is a binary 1 if all the received bits are also binary 1. When an AND gate receives two bits or logical voltages, the AND gate logically ‘ands’ the bits to form the output.
An OR gate is a logic circuit that has at least two inputs each capable of receiving a bit, wherein the output of the OR gate is a binary 1 if any of the received bits are binary 1. When an OR gate receives two bits or logical voltages, the OR gate logically ‘ors’ the bits to form the output.
It would be helpful to be able to flush or transfer data from first cell or entry of the scan register to an adjacent cell without removing the data from the first cell. Moreover, in a chain of such cells, it would be convenient to flush bits for every other cell.